VHDL_SOURCE = buttons.vhdl bcdcounter.vhdl monthlength.vhdl clocktime.vhdl \
	alarmtime.vhdl timeset.vhdl dateset.vhdl display.vhdl clockstate.vhdl \
	lcd_commands_pkg.vhdl lcd_data_pkg.vhdl lcd_data.vhdl lcd_if.vhdl \
	lcd_control.vhdl lcd.vhdl clock.vhdl

TB_SOURCE = std_logic_textio.vhdl vhdl2008.vhdl lcd_model.vhdl
	
TESTBENCHES = tb_buttons tb_bcdcounter tb_clocktime tb_timeset tb_dateset \
	tb_display tb_clock

all: syntax_check run_tbs

clean:
	rm *.o *.cf *.ghw $(TESTBENCHES) *.rpt *.summary *.sof *.pof filelist

# ----- GHDL simulator -----

syntax_check: $(VHDL_SOURCE) $(TB_SOURCE)
	ghdl -a $(GHDL_ARGS) $^

tb_%: tb_%.vhdl $(VHDL_SOURCE)
	ghdl -a $(GHDL_ARGS) $<
	ghdl -e $(GHDL_ARGS) $@

run_tbs: $(TESTBENCHES)
	# Make a dummy symlink because of path differences vs. modelsim.
	ln -nsf . implementation
	
	@$(foreach test, $^, \
	echo; \
	echo ---------- $(test) -------- ; \
	./$(test) --wave=$(test).ghw; \
	) true

# ----- Altera Quartus synthesis -----

PROJECT = de2_clock

filelist: Makefile
	rm -f filelist && \
	echo --source de2_fpga_top.vhdl >> filelist; \
	for file in $(VHDL_SOURCE); \
	do echo --source $$file >> filelist; \
	done

$(PROJECT).map.rpt: filelist $(PROJECT).qdf $(VHDL_SOURCE)
	quartus_map $(MAP_ARGS) -f filelist $(PROJECT)

$(PROJECT).fit.rpt: $(PROJECT).map.rpt
	quartus_fit $(FIT_ARGS) $(PROJECT)

$(PROJECT).sta.rpt: $(PROJECT).fit.rpt
	quartus_sta $(PROJECT)
	
$(PROJECT).sof: $(PROJECT).fit.rpt $(PROJECT).sta.rpt
	quartus_asm $(ASM_ARGS) $(PROJECT)

program: $(PROJECT).sof
	quartus_pgm -m JTAG -c 1 -o p\;$(PROJECT).sof