VHDL_SOURCE = PythonProc.vhdl MainStack.vhdl MainStack_tb.vhdl

MAP_ARGS = --family=CycloneII
FIT_ARGS = --part=EP2C35F672C6
ASM_ARGS =
GHDL_ARGS = -g -P../lpm/

PROJECT = PythonProc

all: $(PROJECT).sof

clean:
	rm -rf filelist *.rpt *.chg smart.log *.htm *.eqn *.pin *.sof *.pof db
	rm -f *.o *.cf *\~
	rm -f mainstack_tb

# -------------------------------------------
# -------------- ALTERA QUARTUS -------------

filelist: Makefile
	rm -f filelist && \
	for file in $(VHDL_SOURCE); \
	do echo --source $$file >> filelist; \
	done

$(PROJECT).map.rpt: filelist $(PROJECT).qdf $(VHDL_SOURCE)
	quartus_map $(MAP_ARGS) -f filelist $(PROJECT)

$(PROJECT).fit.rpt: $(PROJECT).map.rpt
	quartus_fit $(FIT_ARGS) $(PROJECT)

$(PROJECT).sof: $(PROJECT).fit.rpt
	quartus_asm $(ASM_ARGS) $(PROJECT)

program: $(PROJECT).sof
	quartus_pgm -m JTAG -o p\;$(PROJECT).sof

# -----------------------------------------------
# --------------- GHDL Simulator ----------------

mainstack_tb: MainStack.vhdl MainStack_tb.vhdl
	ghdl -a $(GHDL_ARGS) $^
	ghdl -e $(GHDL_ARGS) $@