Register map
Zero
General, saved
General, not saved
Python ALU status

0   r0  Zero
1-3 s0-s2  General, saved
4-6 t0-t2  General, not saved
7   stat   Python ALU status

Data transfer, python -> dlx
6 ltype dest, n  Load type field from TOSn
6 lbool dest, n  Load LSB from TOSn

Data transfer, dlx -> python
3 stype src      Set type field for TOS from register
8 stypei imm.    Set type field for TOS from immediate
1 sbool imm.     Set LSB for TOS

Data transfer, stack
6 pop  src0, src1    Push/pop two registers to/from hardware stack
6 push dest0, dest1

Arithmetic/logic
9 and/xor dest, src0, src1      And/xor two registers
11 andi, xori reg, imm.     And/xor with immediate

Control
13 beqz, bnez     Branch to 13bit address based on register
13 bra            Branch to 13bit address always
13 call           Jump to 13bit address and store return address
0  return         Reload return address

Instruction format (DLX)